Magnetic tape data processing system

ABSTRACT

There is disclosed a data handling system for use as a terminal or word processor including input-output means, intermediate memory and a magnetic tape cassette principal memory. Incoming data is accumulated alternately in one of the intermediate memories until its capacity is reached, then the data block is transferred to the principal memory at a high speed. An inverse sequence is followed for playback. For data editing, a special editing memory and associated control logic are provided. Blocks of data are transferred from the principal memory to one of the intermediate memories. The data is entered in the editing memory either continuously or on a character-by-character basis controlled by the user. Data may be added or deleted as desired, after which, individual data blocks are returned to the principal memory. (Space in the latter is automatically allowed when data is recorded to accommodate added characters.) During editing, line length adjustment is provided by converting &#39;&#39;&#39;&#39;spaces&#39;&#39;&#39;&#39; near the end of an edited line into &#39;&#39;&#39;&#39;carrier returns&#39;&#39;&#39;&#39;. Carrier returns far from the end of an edited line become &#39;&#39;&#39;&#39;spaces&#39;&#39;&#39;&#39;. Search capability based on selectable identifying characters, both in forward and reverse directions of tape travel is also available. Searches may be part of the editing operation or simply in preparation for editing or a normal playback.

United States Patent [1 1 Spademan et a1.

Oct. 9, 1973 MAGNETIC TAPE DATA PROCESSING SYSTEM lnventors: Charles F. Spademan, North Worthington; Joseph P. Marsalka, Columbus, both of Ohio Assisnw MhQQlBQPBaQP Q Filed: Aug. 9, 1972 Appl. No.: 279,070

Related U.S. Application Data Continuation-impart of Ser. No. 203,245, Nov. 30, 1971, and a continuation-impart of Ser. No. 123,187, March 11, 1971.

[52] U.S. Cl. 340/1725 [51] Int. Cl. Gllb 27/02 [58] Field of Search 340/1725 [56] References Cited UNITED STATES PATENTS 3,618,032 11/1971 Goldsberry et al. 340/1725 3,610,902 10/1971 Rahenkamp et al.. 340/1725 3,569,940 3/197] McFadden et al 340/1725 3,346,853 10/1967 Koster et al. 340/1725 Primary Examiner-Gareth D. Shaw Attorney-Robert E. Leblanc et al.

[57] ABSTRACT There is disclosed a data handling system for use as a terminal or word processor including input-output means, intermediate memory and a magnetic tape cassette principal memory. Incoming data is accumulated alternately in one of the intermediate memories until its capacity is reached, then the data block is transferred to the principal memory at a high speed. An inverse sequence is followed for playback.

During editing, line length adjustment is provided by converting spaces" near the end of an edited line into "carrier returns". Carrier returns far from the end of an edited line become spaces".

Search capability based on selectable identifying characters, both in forward and reverse directions of tape travel is also available. Searches may be part of the editing operation or simply in preparation for editing or a normal playback.

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1 MAGNETIC TAPE DATA PROCESSING SYSTEM INTRODUCTION AND BACKGROUND The present application is a continuation-in-part of copending application Ser. No. 203,245 filed Nov. 30, I97] entitled Magnetic Tape Data Handling System Employing Dual Data Block Buffers, which application is, in turn, a continuation-in-part of copending application Ser. No. l23,l87, filed Mar. ll, i971 entitled Magnetic Tape Data System. This application itself is a continuation-in-part of said application Ser. No. 123,!87. The disclosures of said applications, Ser. No. l23,l87 and Ser. No. 203,245, are fully incorporated by reference herein.

Our aforementioned parent applications are directed to so-called terminal equipment" used for data transmission, for obtaining access to, and for controlling a computer. This invention relates to such terminals which provide capability for editing, correcting, updating, augumenting, or otherwise changing previously stored data, which is relatively inexpensive, reliable and durable, and sufficiently versatile, to be compatible with commonly used information transmission and processing formats, and data transmission rates.

Editing is best accomplished locally and off-line" since it is a fairly slow real time operation. The capabilities of the equipment here disclosed are particularly adapted to complement our aforementioned terminal systems, but the principles of the invention are readily adapted to comparable terminal systems of other kinds.

With systems of the type in question, a letter or other message is prepared in draft and stored in a suitable memory medium. For editing, the original draft is retrieved, and the necessary corrections are inserted. No new draft is made, but the corrections are entered in the memory for subsequent retrieval to prepare the final draft (or for further revision),

Operational features required for highly flexible editing include automatic playback for rapid advance through the message individual character-by-character playback to reach a particular character for correction, multiple character insertion, and deletion. The latter should include deletion of an individual character, or character group such as words, sentences, lines etc. Additionally since the editing operation is likely to change line lengths, capability should exist for adjusting lines by converting spaces to carrier returns and vice versa to assure lines in the edited text of the proper length.

Also desirable is a search operation by which a message characterized by a selectable multiple character identifier code may be located in the data memory. For editing, this would be a high speed playback of con trolled length.

So far as applicants are aware, all heretofore proposed and available systems providing full scale editing and data formatting functions employ two separate memory systems, one containing the original raw or draft data, and the other receiving the edited data so that the end of the editing operation, the entire revised message is contained in the second memory. Such an arrangement, while workable, possesses several important practical disadvantages.

For example, if a punched paper tape is used as a memory medium, then each revision requires a new, and non-reusable tape. Where a magnetic tape is used as a memory medium, the latter disadvantage is avoided, but offsetting this are the duplication of mechanical equipment for the tape transport, and inherent technical and economic factors making the tape transport itself one of the weakest links in the entire system. Moreover, irrespective of the type of memory medium, use of a second tape is an inconvenience and a complication for the operator both during training, and thereafter during routine use.

In accordance with the present invention, we have discovered that by appropriate utilization of solid state memory equipment, and proper data formatting, the multiple tape memory arrangement of prior systems can be dispensed with, and with the need for duplicate data handling equipment including tape transport, playback and record circuitry, etc. Indeed, by judicious choice of components, and system organization in accordance with this invention, it has been found possible to provide the data editing and formatting capabilities of the most expensive currently available systems at a substantially reduced cost and without the need for the inconvenience and complexity of the multiple memories previously employed.

All of the desirable data processing features mentioned above, including individual character, word, and line deletion, character substitution, and augumentation, character-by-character playback and controlled continuous playback, and even line length adjustment are inexpensively provided. The system also provides for counting the number of typed lines while the original draft is being prepared to permit control of the length of a typed page. Also provided is facility for inserting a gap in the principal memory for storage of data added during an editing operation.

All of the foregoing functions are accomplished in accordance with this invention by the utilization of a data accumulator or editing memory having a capacity for storing a large number of characters, for example, about L000. For the editing operation, data is transferred from the principal memory to the editing memory in data blocks of some convenient size. This is preferably accomplished by use of an intermediate memory unit as described in our above-mentioned parent applications. Data is transferred from the intermediate memory under operator control and is halted whenever a correction or addition is to be made. Line length adjustment proceeds automatically. After editing, the data block is returned to the tape through the intermediate memory and stored in the same place on the tape from which it was removed.

if the editing operation results in deletion of part of a data block, then storage is not effected until there is accumulated in the editing memory enough data to form a complete data block. if the editing operation results in augumenting the data block, then only that part of the accumulated data forming one data block is returned to the tape. The remainder is retained in the accumulator, and becomes part of the next data block to be returned to the tape. the aforementioned process continues with excess data accumulating in the editing memory until the editing process for an entire message is completed, after which any remaining data is stored in the expansion space provided on the tape for this purpose. The editing operation is controlled by circuitry described below, in conjunction with a read only memory (ROM) in which reference characters such as carriage return, spaces, etc. are stored. The various functions of the terminal equipment described in our parent application are retained, and in addition the capability is provided for backward, as well as forward search.

OBJECTS OF THE INVENTION Accordingly, it is among the objects of this invention:

to provide an improved magnetic tape data storage and processing system or use as a data terminal and local message preparation and editing center;

to provide a keyboard controlled magnetic tape data processing machine which is simpler and less expensive than currently available devices, yet reliable and capable of providing a wide range of data editing and augmenting functions;

to provide a magnetic tape data processing system having data editing capabilities in which information is transferred to and from the principal tape memory for editing in large data blocks, and processes in an accumulator or temporary editing memory, and is thereafter returned to the principal memory;

to provide a data editing system in which data is transferred from the tape memory to an editing memory through an intermediate memory unit;

to provide such a system in which data is played into the editing memory from the intermediate memory unit under control of the operator, on a character-bycharacter basis, or continuously, until halted, either manually upon recognition of a preselected character combination;

to provide a data editing system in which data correction in the editing memory is effected by adding one or more characters by means of an external keyboard device, either serially or in parallel;

to provide a data editing system including a read only memory for storing a number of reference characters used during various data deletion operations to permit identification of the reference characters as part of the data to be deleted;

to provide a data editing system permitting line adjustment to accommodate increase or decreases in number of characters in message;

to provide such line adjustment by converting spaces near the desired end of an edited line to carrier returns, and converting carrier returns remote from the desired end of a line into spaces;

to provide such line adjustment in which carrier returns at the end of a paragraph are not converted to spaces even if they appear remote from the desired line end; and

to provide a data editing system capable of search of the principal memory for a desired character combination in either direction on the tape, and in the forward direction as part of the editing operation,

The exact nature of this invention, together with other general and specific objects and advantages thereof, will be apparent from consideration of the following detailed description and the accompanying drawings.

BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is an overall block diagram of an editing subsystem according to the invention in a data terminal as disclosed in our parent application Ser. No. 203,245;

FIGS. 2A and 3A show the actual circuitry in block form with signal flow paths for data included;

FIGS. 25 and 3B show in chart form the control signal input to and from the circuit blocks;

FIGS. 4A 4G show the operating characteristics of certain circuit elements employed in the system;

FIG. 5 is a detailed circuit diagram of the system input-output logic;

FIG. 6 shows the programming logic;

FIG. 7 shows the details of the input/output register, the associated control logic and the Read Only Memory;

FIG. 8 illustrates the details of part of the operating mode selection logic;

FIG. 9 illustrates the details of the tape memory operation control logic;

FIGS. 10 and 11, arranged as shown in FIG. 12, illustrate the construction of the intermedite memory and associated control logic, together with part of the data format control logic; and

FIGS. 13 16 show the details of the edit mode selection logic, the edit control logic, the editing memory, and the ROM control logic.

For convenient reference and correlation between the detailed description and the drawings, a reference numerical scheme has been adopted wherein the first digit or digits represent the FIGURE number on which the reference numeral first appears. Thus, an item bearing the reference numeral 604 first appears on and is described in connection with FIG. 6, and items bearing the reference numerals 1208 and 1294 first appear on and are described in connection with FIG. 12.

OVERALL SYSTEM ORGANIZATION (FIG. I)

The data editing subsystem is incorporated in a data terminal as described in our parent applications, but description of the overall system will be omitted, where possible. The reader is referred to our parent applications for such information if it is desired. Briefly, however, with reference to FIG. I, a terminal or data handling system of the type with which this inventin is to be used includes an input/output printer 102, a communication line coupler or modem 104 to interface with a communication channel, such as a telephone or telegraph line, a temporary data storage and processing unit 106, a principal memory unit I08 preferably including a magnetic tape cassette drive, and an associated magnetic tape cassette as the memory medium, and an editing memory 110.

Printer 102 may be a serial machine such as a teletype". Since the terminal is directly compatible with such a machine, a customer already possessing or preferring a teletype may readily convert the same into a tape storage terminal with all the attendant benefits of this invention.

Where letter writing or other typing functions are a principal intended use, a more versatile printer, such as that described and claimed in assignees copending U. S. Patent applications Ser. No. 79,202 filed Oct. 8, I970 entitled Input-Output Typewriter Apparatus; Ser. No. 98,627, filed Dec. 16, 1970, entitled Solenoid Drive Circuit; and Ser. No. 101,502, filed Dec. I970, entitled Improved Solenoid Drive Circuit is preferred. The latter is a parallel machine, and the equipment described is directly compatible with these, as Well as with the serial machines.

Data storage and processing unit 106 is comprised of an input-output (I/O) uit 112 including an input/output buffer and required control logic, connected to printer 102 by cable 114, and to coupler I04 by cable 116. Data storage and processing unit 106 also includes a pair of intermediate memory units 118A and B, connected respectively to input/out unit 112 by coupling unit 120 and to tape memory unit 108 by coupling unit 122. Each intermediate memory unit is preferably constructed of one or more random access memory units (RAM s) providing a data capacity of at least 1,280 bits per unit. While two RAMs are preferred, a single one may be provided, as in our parent application Ser. No. 123,187.

Editing memory 110 is also preferably comprised of RAM units, and advantageously should provide substantially greater storage capacity than expected for the majority of anticipated editing operations. A capacity of about 1,000 characters is preferred, but more may be provided where desired, if the resulting cost increase is acceptable. The editing memory is associated with one of the intermediate memories such as 118A if two are used, but data transfer is provided through coupling unit 120, and [/0 unit 112 as indicated by signal path I24, and as described in detail below.

The principal memory includes the actual tape transport (not shown) and record and playback circuits. Preferably separate tape tracks are provided, one for data and one for timing control pulses. Separate record circuits 126 and 130, and playback circuits 127 nd 132, couple the data and timing control pulses respectively to and from the tape.

A main control logic unit 134 is coupled to the system components mentioned above by signalling path 136 while a set of manual control inputs collectively denoted 140 provide external comman input capabil ity. External controls for the various system operations are mounted on an auxiliary keyboard or control panel (not illustrated) on printer 102 or otherwise within convenient reach of the operator The tape unit may be part of a console containing the system electronics.

DETAILED FUNCTIONAL DESCRIPTION FIGS. 2A and 3A show the actual circuity in block form with signal flow paths for data included. FIGS. 28 and 3B show in chart form the control signal input to and from the circuit blocks.

Referring to FIGS. 2A and 3A, there are shown an input/output unit 202, a three character (24bits) shift register 204, and a shift register control unit 206, a character identification unit 218, an intermediate memory control unit 222, an operating mode selection unit 302, a tape control unit 304, a master sequence control unit or programmer 306, a pair of master oscillators 308 and 310, an associated frequency selection and division unit 312, and an editing control unit 301. Also illustrated in FIG. 2A are intermediate memory units 118A and 1188, and read only memory unit (ROM) 138. FIG. 3A also illustrates the editing memory 110.

Broadly stated, input/output logic unit 202 receives incoming serial data over a lead 208, and provides the same over a lead 210 to the serial input of shift register 204. Parallel input data is received from a local source over leads 212a through 212]", and after suitable input processing, is provided over leads 214 to the parallel inputs of the shift register. Parallel inputs to the shift register are also provided by ROM 138, as explained below for carrier return/space conversion and EOM" code insertion.

Parallel outputs are provided by the shift register over 24 leads 216a-216x. These are provided to the character identification unit 218 described below for use during search and edit operations. Also, the first eight bits on leads 216a-h, are provided to input/output unit 202 for utilization during local playback operation. The eighth bit alone, representing a serial output of the shift register in provided to the input/output unit on the lead 216/: from which it is transferred serially to an intermediate memory control unit 222 over lead 224 for temporary storage in one of intermediate memory units or to appropriate serial utilization equipment over lead 226 during playback. Lead 226 also provides the data input to editing memory for the edit operation.

For data output or playback" operation, data is coupled serially from intermediate memory units 118A or B to input/output unit 202 over a lead 228 and then the shift register input over lead 210. The shift register data output is provided in parallel over leads 216 as previously noted, and then to printer 102, over a set of parallel leads 230.

As noted above, each of intermediate memory units 118A and B provides temporary storage for 1280 data bits before transfer to the tape memory in the record modes, or to other portions of the system in the playback, search", or edit" modes. For all operations except editing, data is stored alternately in each unit; while one unit receives data, the other emits data previously stored. For editing, only memory unit 118A is employed. Memory unit operation, including selection of the memory unit to receive data, is controlled by memory control unit 222.

Referring to FIGS. 1 and 2A, data transferred to the tape memory is provided to data record circuit 126, while data from the tape is provided by data playback circuit 128 over lead 242. correspondingly, timing control signals are provided to record circuit 130 over lead 244, and control signals from the tape are provided by playback circuit 132 over lead 246.

Mode selection unit 302 provides selective actuating signals for the system as required to establish and maintain operation in the record, playback, and search modes. Tape control unit 304 includes the forward and reverse tape drive mechanism and other portions of the system required to transfer information to and from the data and timing tracks on the tape. Sequence control unit 306, master clocks 308 and 310, and frequency selection and division unit 312 provide the sequence of control signals to effect transfer of information between the memory units, and into and out of the system, and to initiate the required data processing operations, as hereinafter described in detail.

Edit control unit 301, ROM 138 and editing memory 110 control the editing functions and the length of a typed page as described in detail hereinafter. For this purpose, ROM 138 stores the reference characters (space, period, etc.) used in the edit operation, and the end of message (EOM) character. These are used for character identification during the skip functions, and for carrier return/space interchange during line length adjustment. ROM 138 also provides the EOM code word for tape storage when needed.

Control signals for the above described operations are coupled between the various circuit units in the manner indicated in FIGS. 28 and 38. The exact nature of the signals involved will be more meaningful after consideration of the detailed construction of the system subunits, and description is deferred for this reason. Logic Elements Operation is described in terms of various conventional logic elements as illustrated in FIGS. 4(a) through (g).

FIG. 4(a) shows a two-input NAND gate. The output is low if and only if both inputs are high. Conversely, the output is high if either input is low. As is well known, utilization of both the conjunctive (low) and the disjunctive (high) aspects of the NAND function allows implementation of any combinational logic function. This approach is followed here.

To distinguish the two functions, the logic device of FIG. 4(a) is used to represent the conjunctive and is referred to as a NAND gate. FIG. 4(b) shows a conventional NAND gate providing the disjunctive function, for which the output is high if either or both inputs are low. This is actually an OR logic function with inverted inputs and will be so referred to. For convenience, the designation OR" will be used. FIGS. 4(c) and 4(d) respectively show conventional inverter, and EXCLU- SIVE OR circuits, while FIGS. 4(e) and 4U) show two types of bi-stable multi-vibrators or flip-flops. FIG. 4(e) shows a set-reset flip-flop comprised of a pair of cross coupled OR* gates having a set input designated S, a reset input designated R and a pair of complementary outputs designated ONE and ZERO. A single block representation of the same unit is also shown, along with a truth table containing the inputs and outputs for the meaningful operating states.

FIG. 4(f) shows a .l-K flip-flop having a pair of signal inputs designated .l and K, clock input designated C, reset input designated R, and two complementary outputs Q and O. A truth table indicating the relationship between the previous output states designated Qn-l, the output state On after time tn (the time the clock input returns low) and the J and K inputs is also shown in FIG. 4(1).

FIG. 4(g) shows a mono-stable or single shot multivibrator. A high level at the set or S input produces a high signal at the output, and a low signal at the Q output for a delay period d, determined by the choice of the circuit parameters. At the end of the delay period, the circuit returns to its rest state with a low signal at the 0 output and a high signal at the 6 output. If the circuit is retriggered by input transition during the delay period, it remains set until input transitions fail to occur for a time exceeding the delay time. Then, the outputs return to their respective rest conditions.

Additional logic units, such as conventional counters, decoders, shift register units, and the read only and random access memories will be described and/or identified as appropriate throughout the following description.

Input/Output Unit. (FIG.

Considering now the details of the invention, inputs from a parallel data source are provided in an eight-bit format, including six character code bits, a parity bit and an eighth bit for compatibility with other code formats having seven information bits, plus a parity bit. These are provided over leads 502(a) through 502(k) to eight NAND gates 504(a)-504(h), controlled by an ENTER DATA signal from the data source.

A second set of eight parallel signals is coupled over leads 732(a)-(h) to eight NAND gates, 508(a)-508(h) from ROM 138. Control for NAND gates S08 is provided by an OR" gate 510, which, in turn, receives as inputs, the EOM STROBE and ROM ENTER signals from mode selection unit 302, and edit control unit 301, respectively. Data is stored in the read only memory in a negative true logic format and is converted to a positive logic format by inverters S16(a)-(h).

NAND gates 504(a)(h) and 508(c)(h) are coupled to eight OR* gates 5l8(a)518(h), the outputs of which are coupled over leads 2l4(a)2l4(h) as the parallel inputs for bit positions 1 through 8 of shift register 204 [See FIG. 2.]

Serial inputs are provided remotely through a suitable coupler, or locally by a serial input unit such as a teletypewriter. The serial input data is coupled through a pair of fixed contacts of ON LINE-LOCAL selection switch 520 and a suitable input signal shaping circuit 522 to a NAND gate 524, controlled by a RECORD signal over lead 526, from mode selection unit 302.

The output of signal shaper 522 also provides the SE- RIAL START signal on lead 528, which actuates sequence control unit 306 to transfer the incoming serial information through shift register 204 and into one of memory units 118A or B for storage. NAND gate 524 is coupled to an OR* gate 530, the output of which is connected over lead 210 as the serial input to shift register 204. [See FIG. 2.] The other input to OR* gate 530 is provided by the output of one of the memory units over lead 228.

Input/output logic unit 202 also provides for selective gating of information from the shift register to one of memory units 118A or B when the system is operating in the RECORD mode. This is accomplished by a NAND gate 532 which receives as inputs, the TAPE STORE signal from mode selection unit 302 and the output of the eighth bit position of shift register 202 over lead 216/1. Lead 216i: is also OR-tied to a lead 534 which provides the I76 CLAMP signal from edit control unit 301. This signal is high (and thus without effect) except during a special memory formatting sequence which simplifies certain operations following entry of an EOM character during a record sequence. [This is described more fully in connection with FIGS. 10 and 11 below.] The low level on lead 534 inhibits NAND gate 532 and maintains its output on lead 224 high irrespective of the data output of the [/O register on lead 2l6h. The NAND gate output on lead 224 (see FIG. 2) provides the signal input to memory unit 118A or B.

Data outputs are provided either to a parallel printer, or serially to a teletype printer or to a suitable data coupler. For a parallel printout, the shift register data at the 1st eight bit positions, processed as described in our parent applications, is provided to the printer data input terminals Thereafter, the shift register is actuated, and a new code word is shifted serially from one of the intermediate memory units through OR gate 530, and the parallel printout is repeated. Serial output data is provided through an output circuit 546, described below. A printout sequence is initiated by a START PRINTOUT CYCLE signal, generated by a NAND gate 536. This receives as its inputs, the PLAY signal from mode selection unit 302, and an output, denoted No. 6, from sequence control unit 306, indicating previous serial shift cycle to be completed. An addition input, denoted UTILIZATION DEVICE READY, indicating that the data receiving unit is ready to accept further data, is provided by the output printer or by the data coupler.

The W5 signal actuates the internal operations for shifting data from the intermedi- 

1. Processing means for digital data in the form of multibit character code words comprising: a principal memory having a magnetic tape as the memory medium; input-output means; an intermediate memory having capacity for storing a data block comprising a plurality of code words; an editing memory having capacity for storing a plurality of data blocks substantially less in number than the principal memory; and editing operation control means including means to effect transfer from said principal memory to said intermediate memory of a single block of data, means for transferring data from said intermediate memory to said editing memory, first logic means responsive to external commands to control the quantity of data transferred from said intermediate memory, second logic means responsive to external commands transferring data from said intermediate memory while inhibiting said editing memory to prevent storage of data transferred thereto from said intermediate memory, third logic means for actuating said editing memory to receive data from an external source through said input-output means, fourth means responsive to transfer of said data block from said intermediate memory and to accumulation of complete data block in said editing memory to transfer a complete data block from said editing memory back to said principal memory through said intermediate memory, and means responsive to transfer of said data block to said principal memory to transfer the next unedited data block to said intermediate memory.
 2. A data processor as defined in claim 1 wherein said first logic means includes first means responsive to an external command for transferring data from said intermediate memory continuously until halted bY a further external command, and second means responsive to another external command to transfer a single character code word from said intermediate memory.
 3. A data processor as defined in claim 1 wherein said second logic means includes means responsive to a first external command to transfer a single character code word from said intermediate memory, and means responsive to other external commands for transferring data continuously from said intermediate memory, means to identify certain characters being transferred from said intermediate memory, and means responsive to particular external commands to halt transfer of data from said intermediate memory upon identification of an associated one of said certain characters.
 4. A data processor as defined in claim 3 further including buffer means coupling said intermediate memory and said editing memory, and adapted to receive data one bit at a time, and wherein said identifying means comprises a read only memory for storing the code words for said certain characters, data comparison means coupled to said read only memory and to said buffer means, and operative to provide an indication whenever data coincidence is detected, means for scanning the addresses of said read only memory at a rate substantially exceeding the input bit rate to said buffer, and means responsive to a coincidence indication to identify the particular read only memory address for which said coincidence occurred.
 5. A data processor as defined in claim 1 further including fifth logic means responsive to an external command and to incoming data from said input-output means to store a search reference code, means responsive to completion of storage of said reference code to initiate continuous transfer of data from said intermediate memory, and identification means for comparing the data being transferred from said intermediate memory and for halting said transfer upon recognition of said reference code.
 6. A data processor as defined in claim 1 wherein said fourth logic means includes means responsive to transfer of a complete data block from said intermediate memory and accumulation of less than a complete data block in said editing memory for transferring the next unedited data block from said principal memory to said intermediate memory.
 7. A data processor as defined in claim 1 wherein a plurality of data blocks comprising a complete message carries a particular terminal code word and wherein said fourth logic means includes means responsive to the entry of saiD terminal code word into said editing memory to transfer all data in said editing memory to said principal memory through said intermediate memory.
 8. A data processor as defined in claim 1 including adjusting means for establishing a printout line length format, means for counting the number of characters stored in the editing memory since the end of a previous line and to provide an indication when a predetermined number has been counted, means for identifying first and second character code words being transferred out of said intermediate memory, means for generating the code words for said first and second characters, means responsive to identification of said first character in the absence of said predetermined count indication to suppress entry of said first character in said editing memory and to actuate said generating means to enter the code word for the second character into the editing memory, and means responsive to identification of said second character in the presence of said predetermined count indication to suppress entry of said second characters in said editing memory and to actuate said generating means to enter the code words for the first character into the editIng memory.
 9. A data processor as defined in claim 8 further including means responsive to identification of either said first or said second characters to suppress operation of said adjusting means for the immediately following character transferred from said intermediate memory.
 10. A data processor as defined in claim 8 wherein said means for identifying said first and second character code words includes buffer means coupling said intermediate memory to said editing memory, and operable to receive data one bit at a time, a read only memory containing the code words for said first and second characters, data comparison means coupled to said read only memory and said buffer and operative to provide an indication whenever data coincidence is detected, means for scanning the addresses of said read only memory to render accessible to said data comparison means all the data stored in said read only memory, said scanning occurring at a rate substantially exceeding the input bit rate for said buffer, and means responsive to said coincidence indication to identify the particular read only memory address for which coincidence occurred.
 11. A data processor as defined in claim 10 wherein said generating means comprises said read only memory and the addressing means therefor, the latter being actuated when one of said first or second characters is to be generated, and also including logic means responsive to generation of said first or second character as required to halt the operation of said addressing means.
 12. A data processor as defined in claim 1 further including a read only memory for storing code words for a plurality of characters and addressing means for said read only memory comprising counting means having a rest state and a plurality of active states.
 13. A data processor as defined in claim 12 including buffer means, means for coupling said buffer means to the input or the output of said intermediate memory, switching means for coupling the output of said read only memory to the input of said buffer means, and means for entering a code word from said read only memory into said buffer means comprising logic means responsive to a command to actuate said addressing means, and means responsive to a particular address being reached for actuating said switching means and said buffer means to receive in the latter, the read only memory output.
 14. A data processor as defined in claim 1 wherein said editing operation control means includes means for establishing a sequence of editing modes, a first mode being established responsive to an external command, said control means being responsive to establishment of said first mode to transfer said block of data to said intermediate memory from said principal memory, means responsive to transfer a complete block of data to said intermEdiate memory for establishing a second editing mode, said control means being responsive to establishment of said second mode and to the various external commands to transfer data out of said intermediate memory, said fourth logic means being operative to establish a third editing mode during which data is returned to said intermediate memory, followed by a fourth mode during which data is transferred from said intermediate memory to said principal memory, and responsive to completion of said fourth mode or to transfer of a complete data block from said intermediate memory, and accumulation of less than a complete data block in said editing memory to return said system to said first editing mode.
 15. A data processor as defined in claim 14 Wherein a plurality of data blocks comprising a complete message carries a particular terminal code word, and wherein said fourth logic means includes means for sensing said terminal code word, as it enters said editing memory when said system is operating in said second editing mode and responsive thereto to transfer said system to said third mode, and thereafter to cycle said system between modes three and four, means for sensing when all data in said editing memory has been transferred to said intermediate memory, and for terminating editing operation at the end of the mode four state following such transfer.
 16. A data processor as defined in claim 14 wherein said principal memory includes a tape transport, a playback head and a record head disposed upstream of said playback head, wherein data is stored in said principal memory with gaps separating successive data blocks, and including means responsive to entry of the system into editing operation to reverse said tape transport until the tape is positioned with the playback head at the beginning of the first data block to be edited, and for thereafter establishing the system in said first editing mode.
 17. A data processor as defined in claim 16 including means responsive to termination of editing operation and immediate reestablishment thereof with no intervening operation to inhibit the tape reversal prior to establishment of said first editing mode.
 18. A data processor as defined in claim 14 wherein said principal memory includes a tape transport, and playback and record heads, and including means responsive to entry of the system into said second editing mode to reverse said tape transport until said tape is positioned with said record head at the beginning of the data block transferred to the intermediate memory during the immediately previous edit mode one.
 19. A data processor as defined in claim 14 wherein said input/output means includes buffer means coupling said intermediate memory to said editing memory, and means for actuating said buffer means to receive and emit data on a bit by bit basis, and wherein said intermediate memory and said editing memory are each random access memories and each include addressing means comprising counters for rendering accessible the memory sites in a predetermined order for data storage and retrieval.
 20. A data processor as defined in claim 19 including data transfer clock means including first means for generating control pulses in groups equal in number to the number of bits in a code word, and second means for generating a continuous succession of control pulses, and means for operating said intermediate memory, said buffer, and said editing memory in response to said groups of control pulses during edit mode two, and for operating said intermediate and editing memories in response to said succession of control pulses during the other edit modes.
 21. A data processor as defined in claim 20 including means for inhibiting operation of said editing memory for the first group of control pulses generated during each edit mode two to allow data from the intermediate memory to fill the buffer.
 22. A data processor as defined in claim 20 including means for providing data from an external source during edit mode twO to the input of said buffer, means responsive to the provision of a first character code word from said external source for inhibiting data transfer to said editing memory until said first code word has been entered in said buffer, means responsive to entry of an external character code word to actuate said buffer and said editing memory in response to a group of control pulses, and logic means responsive to a first group of control pulses for external data entry following an editing operation other than external entry for reducing the count of the addressing means for said intermediate memory for each pulse of said group, and for thereafter inhibiting operation of said intermediate memory until external data entry ceases.
 23. A data processor as defined in claim 20 including means for generating a signal in response to the addressing means for the intermediate memory corresponding to the last bit of a data block, means responsive to said signal during edit mode two for operating said buffer and said editing memory in response to an additional group of control pulses, and means responsive to the end of said additional group of control pulses for transferring the system to the third edit mode.
 24. A data processor as defined in claim 20 wherein said first logic means is operative only during edit mode two, and includes means responsive to a first external command to operate said intermediate memory, said buffer, and editing memory in response to successive groups of control pulses, and responsive to a second external command to terminate said operation and means responsive to termination of an edit mode two during such continuous operation for reinitiating said continuous during the next edit mode two in the editing cycle.
 25. A data processor as defined in claim 24 wherein said first logic means further includes means responsive to a plurality of additional external commands to operate said intermediate memory and said buffer in response to said groups of control pulses but to inhibit operation of said editing memory, said means being responsive to a first of said additional commands to operate said intermediate memory and said buffer but to inhibit said editing memory for one group of said control pulses, and additional means coupled to said buffer for indicating the presence of certain character code words therein, said first logic means being responsive to others of said external commands to operate said intermediate memory and said buffer and to inhibit said editing memory in response to successions of groups of control pulses until the presence of respective ones of said character code words has been detected, and for one additional group of control pulses thereafter.
 26. A data processor as defined in claim 25 further including means responsive to termination of an edit mode two during one of the aforesaid operations for reinitiating said operation during the next edit mode two in the edit cycle.
 27. A data processor as defined in claim 26 wherein said additional means comprises a read only memory containing said certain character code words in respective memory sites, comparison means coupled to the outputs of said buffer and said read only memory, means for addressing said memory sites in succession, means for operating said addressing means at a rapid rate in relation to the repetition rate of said control pulses, means to generate an indication of a match between the data in said buffer and in said read only memory, and means responsive to said match indication to identify the read only memory address for which said match occurred.
 28. A data processor as defined in claim 24 wherein said first logic means further includes means responsive to another external command to operate said intermediate memory, said buffer and said editing memory for one group of control pulses.
 29. A data processor as defined in claim 19 further including means for entering data from an external source into said buffer, special memory means having its input connected to sAid buffer, means responsive to a special external command for entering said external data into said special memory, means responsive to entry of a desired number of character code words in said special memory during edit mode two for initiating continuous transfer of data from said intermediate memory through said buffer to said editing memory, and for continuing said transfer through successive entries of the system into edit mode two, comparison means coupled to said special memory and said buffer and responsive to a match between the data therein to generate a control signal, and means responsive to said control signal to advance said editing memory, said buffer, and said intermediate memory to transfer one additional character code word to said editing memory.
 30. A data processor as defined in claim 29 including means for inhibiting operation of said editing memory for the first character code word following initiation of said continuous data transfer.
 31. A data processor as defined in claim 20 wherein said editing memory is comprised of a plurality of bit storage sites and addressing means for rendering said sites accessible in sequence for data storage, contents counting means comprising an up down counter, means for advancing said up down counter during edit mode two, and means for reducing the count of said up down counter during edit mode three.
 32. A data processor as defined in claim 31 further including first and second count memories connected to said addressing means for said editing memory, means reponsive to the end of an edit mode two for storing the address of said editing memory site last accessed in said first count memory, means responsive to the end of an edit mode three for storing the address of said editing memory site last accessed in said second count memory, means responsive to the beginning of an edit mode two to set the editing memory addressing means to the address stored in said first count memory, and means responsive to the beginning of an edit mode three to set the editing memory addressing means to the address stored in said second count memory.
 33. Processing means for digital data in the form of multibit code word comprising: a principal memory having a magnetic tape transport for carrying a magnetic tape as a memory medium, playback and recording heads; an intermediate memory for storing a block of data comprised of a plurality of code words; input/output means including a buffer for storing a predetermined small number of code words, means for selectively coupling the input of said buffer to the output of said intermediate memory or to an external data source; special memory means having a capacity equal to those of the buffer; comparison means connected to the outputs of said buffer and said special memory; and search control logic means including means responsive to an external command to connect said buffer to said external source, means responsive to entry of data to said buffer from said external source to store said data in said special memory, means responsive to storage of said data in said special memory to initiate operation of said tape transport and said playback head to load a data block from said tape to said intermediate memory, means responsive to loading of said intermediate memory to couple said buffer to said intermediate memory and to transfer data to said buffer, means responsive to a match between the data in said buffer and that in said special memory to terminate data transfer to said intermediate memory, and means responsive to transfer of an entire data block from said intermediate memory without a data match to operate said tape transport and said playback head to transfer another block of data to said intermediate memory.
 34. A data processor as defined in claim 33 wherein said intermediate memory comprises a random access memory unit and addressing means comprising an up-down counter, said memory being responsive to a particular count to render accessible a corresponding memory site, for data sTorage or retrieval, means for setting said counter at a predetermined initial count, and means for advancing said counter from said initial count, and for actuating said random access memory to store the data output of said tape on a bit by bit basis in successive memory sites, and wherein said means for transferring data to said buffer from said intermediate memory comprises means to set said counter to said initial count, and means for advancing said counter, and for operating said random access memory and said buffer to enter the contents of each memory site in turn into said buffer.
 35. A data processor as defined in claim 34 wherein said tape transport is run so the tape moves in the same direction as when the data thereon was originally recorded, and further including means responsive to said external command and to another external command to operate said tape transport so the tape runs in the direction opposite to that when the data was recorded.
 36. A data processor as defined in claim 35 further including means responsive to said other external command to cause said up-down counter to be set to a count equal to the number of bits in a data block and to operate said counter to reduce the count therein when said random access memory receives data from said tape.
 37. A data processor as defined in claim 36 including means responsive to a data match during an operation initiated by both of said external commands to initiate operation of said tape transport in said normal direction, and storage in said random access memory beginning at the memory site corresponding to the initial count of said counter, and for continuing such operation until a match again occurs between the data in said buffer and said special memory.
 38. A data processor as defined in claim 37 wherein said intermediate memory comprises two separate random access memories and associated addressing means, and further including cycling means operative to permit transfer of data from one of said random access memories to said buffer while data from said tape is transferred to the other of said random access memories. 